An Efficient Parallel Architecture for Wideband Digital Down Conversion ⋆
نویسندگان
چکیده
Intermediate frequency (IF) processing bandwidth has long been a bottleneck, because of the restriction caused by the processing speed of digital signal processing devices. Field programmable gate array (FPGA) can not provide the data processing speed that matches the sampling rate to perform direct wideband digital down conversion. That’s why a parallel architecture, which involves parallel decomposition of numerically controlled oscillator (NCO) and poly-phase decomposition of low pass filter, is presented in this paper. Mathematic expressions of multipath NCO digital local oscillators are especially stressed, and solution space of decomposition factor is also discussed. This presented architecture can effectively reduce operation rate and relieve computational pressure, which will benefit the following baseband signal processing components. Finally, simulation results of MATLAB and experimental platform are presented to illustrate the validity of the architecture.
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